The present invention relates to a ceramic capacitor adapted to be mounted inside a wiring board or on a surface of a wiring board, and relates to such a wiring board.
In recent years, the speed and function of semiconductor integrated circuit chips (IC chips) which are used as a microprocessor in a computer, etc., are increasingly enhanced. Accordingly, a typical IC chip tends to have an increasing number of terminals, and a decreasing pitch between the terminals. Such a typical IC chip has a bottom surface on which a lot of dense terminals are arranged in an array, where the terminals are connected to terminals of a mother board by flip chip mounting. It is however generally difficult to directly connect such an IC chip to a mother board, because IC chip terminals are significantly different from mother board terminals in inter-terminal pitch. Accordingly, such connection is usually implemented by preparing a package where an IC chip is mounted on an IC-chip-mounting wiring board, and mounting the package on a mother board. For such an IC-chip-mounting wiring board, provision of a capacitor is proposed for reduction of switching noise of an IC chip, and stabilization of a supply voltage. For example, Japanese Patent Application Publication No. 2005-39243 shows in FIG. 4 a wiring board in which a ceramic capacitor is mounted in an accommodation hole formed in a core board made of a high polymer material, and the front side and back side of the core board are formed with buildup layers. Japanese Patent Application Publication No. 2007-96262 shows in FIG. 1 a similar wiring board.
FIG. 14 schematically shows a ceramic capacitor 201 according to a reference example. The ceramic capacitor 201 includes a capacitor-forming layer section 202 and a cover layer section 203. The capacitor-forming layer section 202 has a structure in which first internal electrodes 206 and second internal electrodes 207 are arranged alternately, wherein each first internal electrode 206 and one of the second internal electrodes 207 adjacent to the first internal electrode 206 sandwich a ceramic dielectric layer 205 therebetween. Each ceramic dielectric layer 205 is a sintered product of barium titanate as high dielectric constant ceramics, serving as a dielectric or insulator between the first internal electrode 206 and second internal electrode 207.
The cover layer section 203 includes a plurality of ceramic dielectric layers 209 which are layered together. The cover layer section 203 is arranged at an outer surface of the ceramic capacitor 201, covering the capacitor-forming layer section 202. The cover layer section 203 serves for electrical insulation, heat resistance, and moisture resistance of the ceramic capacitor 201.
The ceramic capacitor 201 is formed with a lot of via holes 210 which are arranged in an array spreading all over the ceramic capacitor 201. Each via hole 210 extends through between capacitor major surfaces 213 of the ceramic capacitor 201. In each via hole 210 is provided a first via conductor 211 or second via conductor 212. Each first via conductor 211 extends through the first internal electrodes 206, and electrically connects the same together. Each second via conductor 212 extends through the second internal electrode 207, and electrically connects the same together.
Each capacitor major surface 213 of the ceramic capacitor 201 is provided with first external electrodes 215 and a second external electrode 216 which are placed on the capacitor major surface 213. Each first external electrode 215 is connected directly to an end surface of a corresponding one of the first via conductors 211. The second external electrode 216 is connected directly to end surfaces of the second via conductors 212. The second external electrode 216 is a plane conductor that covers the substantially entire capacitor major surface 213, and includes a plurality of holes such that the second surface electrode 216 is out of contact with the first external electrodes 215. Each first external electrode 215 is a circular conductor that is arranged on the capacitor major surface 213.
When the ceramic capacitor 201 shown in FIG. 14 is mounted inside a wiring board as disclosed in Japanese Patent Application Publication No. 2005-39243, the outer surface of the ceramic capacitor 201 is subject to an external stress due to hardening and shrinkage of a resin and/or due to a history of heating (difference in thermal expansion). The external stress is likely to be concentrated at corner portions 200 each of which is located at a boundary between a capacitor lateral surface 214 and one of the capacitor major surfaces 213. If the ceramic dielectric layers 205 or 209, which are brittle in general, are exposed near the corner portions 200 under a buildup layer 250, it is likely that a crack 221 occurs in the ceramic dielectric layers 205 or 209 near the corner portion 200, and runs in the direction of an arrow F1 as shown in FIG. 15. This can adversely affect the reliability of the wiring board.
In order to prevent the occurrence and development of such a crack 221, it is proposed to layer a dummy electrode 217 between the ceramic dielectric layers 209 for enhancing the toughness of the cover layer section 203, as shown in FIG. 16.